//////////////////////////////////////////////////////////////////////////////////
// Company:        RIT
// Engineer:       Cody Cziesler, Nick Desaulniers
//
// Create Date:    4:36PM 8/1/2011
// Design Name:    Omicron
// Module Name:    omicron_top
// Project Name:   Pipelined CPU
// Target Devices: Xilinx Spartan-3E
// Tool versions:  Xilinx ISE Project Navigator
// Description:    This is the top level verilog file to be synthesized on the Basys 2 Xilinx FPGA
//
// Revision:
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////

`include "include.v"

module omicron_top(
  input wire        rst_n,
  input wire        clk_in,
  output wire [7:0] leds
);

wire clk;
wire clk_n;
wire LOCKED_OUT;

// Clock block
// Instantiate the module
clk_blk i_clk_blk (
  .CLKIN_IN(clk_in),
  .RST_IN(!rst_n),
  .CLK0_OUT(clk),
  .CLK180_OUT(clk_n),
  .LOCKED_OUT(LOCKED_OUT)
);

omicron i_omicron (
  .clk(clk),
  .clk_n(clk_n),
  .rst_n(rst_n),
  .leds(leds[7:0])
);

endmodule
